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Wafer Fab TwinCRE8VIRTUAL's wafer-fab twin runs one recipe three ways: its steps build a cut line across the wafer, the same steps run as lots through a simulated fab line, and the wafer's die are drawn against particles and gate-stack spread. This page reads the bundled runs and recomputes each verdict from its checks.
One CMOS recipe through the cross-section, the fab line and the wafer.
- Status
- pass
- NMOS Vt
- 0.68 V
- PMOS Vt
- -0.66 V
- Die yield
- 88%
- Cycle time
- 4.0 days
- Per good die
- $0.53
pass A pilot-line flow of the late 1980s: LOCOS isolation, 29 nm gate oxide, poly gates, one metal, 5 V.
Checks
28 pass, 0 watch, 0 fault. The run is its worst check.
| Status | Subject | Check | Reading |
|---|---|---|---|
| pass | n-well | litho.NWELL | 3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay |
| pass | active area (opens the field) | litho.ACTIVE | 3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay |
| pass | NMOS threshold adjust | litho.VTN | 3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay |
| pass | polysilicon gate (opens all but the gates) | litho.POLY | 1500 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay |
| pass | n+ source/drain | litho.NPLUS | 3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay |
| pass | p+ source/drain | litho.PPLUS | 3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay |
| pass | contact | litho.CONTACT | 1500 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay |
| pass | metal 1 (opens all but the contacts) | litho.METAL1 | 3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay |
| pass | field oxide | isolation.field_oxide | thinnest field oxide 566 nm; 300 nm keeps a metal line over it from turning the field on |
| pass | NMOS, n+ poly gate | nmos.gate | n+ poly gate; a nmos wants n+ |
| pass | NMOS, n+ poly gate | nmos.channel | channel p-type at 4.0e16 cm⁻³ |
| pass | NMOS, n+ poly gate | nmos.threshold | Vt 0.68 V in [0.50, 0.90] |
| pass | NMOS, n+ poly gate | nmos.junction | source junction 273 nm deep |
| pass | NMOS, n+ poly gate | nmos.leff | 1090 nm effective of 1500 nm drawn |
| pass | NMOS, n+ poly gate | nmos.oxide_field | 1.7 MV/cm across 29 nm at 5.0 V |
| pass | NMOS, n+ poly gate | nmos.contacts | metal on the silicon of source and drain |
| pass | PMOS, p+ poly gate, in the n-well | pmos.gate | p+ poly gate; a pmos wants p+ |
| pass | PMOS, p+ poly gate, in the n-well | pmos.channel | channel n-type at 3.6e16 cm⁻³ |
| pass | PMOS, p+ poly gate, in the n-well | pmos.threshold | Vt -0.66 V in [-0.90, -0.50] |
| pass | PMOS, p+ poly gate, in the n-well | pmos.junction | source junction 295 nm deep |
| pass | PMOS, p+ poly gate, in the n-well | pmos.leff | 1058 nm effective of 1500 nm drawn |
| pass | PMOS, p+ poly gate, in the n-well | pmos.oxide_field | 1.7 MV/cm across 29 nm at 5.0 V |
| pass | PMOS, p+ poly gate, in the n-well | pmos.contacts | metal on the silicon of source and drain |
| pass | bottleneck | line.utilization | the ion implanter group runs 79% busy; queues climb steeply past 85% |
| pass | cycle time | line.x_factor | a lot takes 95 h against 60 h of process: 1.6x |
| pass | line load | line.steady | the last quarter of lots took 0.89x as long as the first |
| pass | die yield | yield.total | 509 good of 576 whole die |
| pass | parametric yield | yield.parametric | 576 of 576 die land every threshold in its window |
Cross-section
i-line stepper, 365 nm, NA 0.5 at 1500 nm drawn features: resolves 438 nm, overlays to 150 nm. The silicon is banded by type between its junctions; dashed lines are junctions.
oxidenitridepolyresistmetaln-type siliconp-type silicon
Transistors
| Device | Gate | Oxide | Vt | Window | Effective length | Source junction | Channel cm⁻³ | Idsat µA/µm |
|---|---|---|---|---|---|---|---|---|
| NMOS, n+ poly gate | n+ | 29 nm | 0.68 V | [0.50, 0.90] | 1090 of 1500 nm | 273 nm | -4.0e16 | 254 |
| PMOS, p+ poly gate, in the n-well | p+ | 29 nm | -0.66 V | [-0.90, -0.50] | 1058 of 1500 nm | 295 nm | 3.6e16 | 149 |
Wafer
| Wafer | 150 mm, 3 mm edge excluded |
|---|---|
| Die | 5.0 × 5.0 mm |
| Whole die | 576 |
| Good die | 509 (88.4%) |
| Defect yield | 88.4% (67 killed) |
| Parametric yield | 100.0% (0 out of window) |
| Defect density | 0.660 /cm² with the edge ring |
| Closed-form yield | Poisson 84.8% · Murphy 85.0% · negative binomial 85.3% |
Fab line
80 lots of 25 wafers through 38 operations: 4.0 days a lot (4.4 at the 90th percentile) against 2.5 days of process, 1.6× raw. 3.69 lots a day, 646 wafers a week, 367 wafers in the line.
| Tool group | Tools × load | Busy | Mean wait | Lots a run |
|---|---|---|---|---|
| oxidation and anneal furnace | 6 × 4 lots | 66% | 0.1 h | 1.01 |
| LPCVD tube | 2 × 4 lots | 60% | 0.3 h | 1.03 |
| sputter coater | 1 × 1 lot | 24% | 0.0 h | 1.00 |
| litho cell | 2 × 1 lot | 44% | 0.1 h | 1.00 |
| plasma etcher | 2 × 1 lot | 65% | 0.3 h | 1.00 |
| wet bench | 2 × 2 lots | 19% | 0.0 h | 1.00 |
| ion implanter (bottleneck) | 1 × 1 lot | 79% | 2.8 h | 1.00 |
| resist asher | 2 × 1 lot | 58% | 0.1 h | 1.00 |
Cost
| Blank wafer | $40.00 |
|---|---|
| Tool time | $226.96 a wafer |
| Masks | $4.00 a wafer |
| Per wafer | $270.96 |
| Per good die | $0.53 |
Process steps (38)
init_oxoxidize dry oxide now 42 nm on 10 of 10 columns screen oxide for the well implantnwell_patternpattern NWELL open over 5 of 10 columns open the n-wellnwell_implantimplant phosphorus 3.5e12 cm⁻² at 150 keV (range 186 nm) reached silicon in 5 of 10 columns phosphorus for the n-wellnwell_stripstrip resist stripped from 5 of 10 columnsnwell_driveanneal 1100 °C for 300 min spreads boron 740 nm, phosphorus 715 nm, arsenic 237 nm drive the well deepinit_ox_etchetch oxide cleared from 10 of 10 columns back to bare siliconpad_oxoxidize dry oxide now 37 nm on 10 of 10 columns pad oxide under the nitridenitridedeposit 100 nm of nitride over every column LPCVD nitride: the oxidation maskactive_patternpattern ACTIVE open over 4 of 10 columnsnitride_etchetch nitride cleared from 4 of 10 columns nitride off the fieldactive_stripstrip resist stripped from 6 of 10 columnsfield_oxoxidize wet oxide now 615 nm on 4 of 10 columns LOCOS: thick oxide where the nitride is gonenitride_stripstrip nitride stripped from 6 of 10 columns hot phosphoric acidpad_etchetch 50 nm off the oxide on 10 of 10 columns pad oxide off the active areasgate_oxoxidize dry oxide now 29–566 nm on 10 of 10 columns the gate dielectricvtn_patternpattern VTN open over 3 of 10 columnsvtn_implantimplant boron 5.0e11 cm⁻² at 25 keV (range 82 nm) reached silicon in 3 of 10 columns boron to raise the NMOS thresholdvtn_stripstrip resist stripped from 7 of 10 columnspolydeposit 400 nm of poly over every column undoped LPCVD polysiliconpoly_patternpattern POLY open over 8 of 10 columnspoly_etchetch poly cleared from 8 of 10 columnspoly_stripstrip resist stripped from 2 of 10 columnsnplus_patternpattern NPLUS open over 3 of 10 columnsnplus_implantimplant phosphorus 5.0e15 cm⁻² at 60 keV (range 74 nm) reached silicon in 2 of 10 columns NMOS source/drain, and the NMOS gate goes n+nplus_stripstrip resist stripped from 7 of 10 columnspplus_patternpattern PPLUS open over 3 of 10 columnspplus_implantimplant boron 3.0e15 cm⁻² at 30 keV (range 99 nm) reached silicon in 2 of 10 columns PMOS source/drain, and the PMOS gate goes p+pplus_stripstrip resist stripped from 7 of 10 columnsilddeposit 600 nm of oxide over every column deposited oxide between poly and metalreflowanneal 950 °C for 30 min spreads boron 39 nm, phosphorus 34 nm, arsenic 13 nm flows the oxide and activates the implantscontact_patternpattern CONTACT open over 4 of 10 columnscontact_etchetch oxide cleared from 4 of 10 columns through the oxide to the source and draincontact_stripstrip resist stripped from 6 of 10 columnsmetaldeposit 800 nm of metal over every column sputtered aluminium; minutes are per wafermetal_patternpattern METAL1 open over 6 of 10 columnsmetal_etchetch metal cleared from 6 of 10 columnsmetal_stripstrip resist stripped from 4 of 10 columnssinteranneal 450 °C for 30 min spreads boron 0 nm, phosphorus 0 nm, arsenic 0 nm forming-gas anneal: ohmic contacts, fewer interface traps
Assumptions
- Each column of the cut line is uniform and independent: no bird's beak, lateral diffusion or etch undercut.
- Effective channel length is the drawn length less 1.5 times the source junction depth.
- Dopants diffuse at their intrinsic rates; no segregation into growing oxide, no enhanced diffusion.
- Implants follow tabulated LSS ranges with no channelling; films stop ions by assumed ratios to silicon.
- Thresholds are long-channel, from the top 100 nm of the channel, with 1e10 cm⁻² fixed oxide charge.
- Mobilities, tool rates, prices and mask life are assumed round figures.
- Tool availability stretches every run; there are no discrete breakdowns or maintenance windows.
- Defect density, clustering and the dirtier edge ring are assumed.
This page reads the bundled runs from CRE8VIRTUAL's virtual-wafer-fab. Nothing is stored, sent or fabricated.