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Circuits

Wafer Fab TwinCRE8VIRTUAL's wafer-fab twin runs one recipe three ways: its steps build a cut line across the wafer, the same steps run as lots through a simulated fab line, and the wafer's die are drawn against particles and gate-stack spread. This page reads the bundled runs and recomputes each verdict from its checks.

One CMOS recipe through the cross-section, the fab line and the wafer.

Status
fault
NMOS Vt
-0.16 V
PMOS Vt
-0.66 V
Die yield
0%
Cycle time
3.5 days
Per good die
no good die

fault The pilot-line flow less its VTN mask: the bare substrate is too lightly doped to hold the NMOS off.

Checks

24 pass, 0 watch, 3 fault. The run is its worst check.

StatusSubjectCheckReading
faultNMOS, n+ poly gatenmos.thresholdVt -0.16 V outside [0.50, 0.90]
faultdie yieldyield.total0 good of 576 whole die
faultparametric yieldyield.parametric0 of 576 die land every threshold in its window
passn-welllitho.NWELL3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay
passactive area (opens the field)litho.ACTIVE3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay
passpolysilicon gate (opens all but the gates)litho.POLY1500 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay
passn+ source/drainlitho.NPLUS3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay
passp+ source/drainlitho.PPLUS3000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay
passcontactlitho.CONTACT1500 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay
passmetal 1 (opens all but the contacts)litho.METAL13000 nm drawn against 438 nm resolved; 750 nm margin against 150 nm overlay
passfield oxideisolation.field_oxidethinnest field oxide 566 nm; 300 nm keeps a metal line over it from turning the field on
passNMOS, n+ poly gatenmos.gaten+ poly gate; a nmos wants n+
passNMOS, n+ poly gatenmos.channelchannel p-type at 1.0e15 cm⁻³
passNMOS, n+ poly gatenmos.junctionsource junction 273 nm deep
passNMOS, n+ poly gatenmos.leff1090 nm effective of 1500 nm drawn
passNMOS, n+ poly gatenmos.oxide_field1.7 MV/cm across 29 nm at 5.0 V
passNMOS, n+ poly gatenmos.contactsmetal on the silicon of source and drain
passPMOS, p+ poly gate, in the n-wellpmos.gatep+ poly gate; a pmos wants p+
passPMOS, p+ poly gate, in the n-wellpmos.channelchannel n-type at 3.6e16 cm⁻³
passPMOS, p+ poly gate, in the n-wellpmos.thresholdVt -0.66 V in [-0.90, -0.50]
passPMOS, p+ poly gate, in the n-wellpmos.junctionsource junction 295 nm deep
passPMOS, p+ poly gate, in the n-wellpmos.leff1058 nm effective of 1500 nm drawn
passPMOS, p+ poly gate, in the n-wellpmos.oxide_field1.7 MV/cm across 29 nm at 5.0 V
passPMOS, p+ poly gate, in the n-wellpmos.contactsmetal on the silicon of source and drain
passbottleneckline.utilizationthe ion implanter group runs 64% busy; queues climb steeply past 85%
passcycle timeline.x_factora lot takes 83 h against 58 h of process: 1.4x
passline loadline.steadythe last quarter of lots took 0.91x as long as the first

Cross-section

i-line stepper, 365 nm, NA 0.5 at 1500 nm drawn features: resolves 438 nm, overlays to 150 nm. The silicon is banded by type between its junctions; dashed lines are junctions.

oxidenitridepolyresistmetaln-type siliconp-type silicon
oxide 566 nmoxide 600 nmfield, westfield_wjunction 273 nmmetal 800 nmNMOS sourcen_srcoxide 29 nmpoly 400 nmoxide 600 nmNMOS gaten_gatejunction 273 nmmetal 800 nmNMOS drainn_drnoxide 566 nmoxide 600 nmfield over the p substratefield_mid_pjunction 2008 nmoxide 566 nmoxide 600 nmfield over the n-wellfield_mid_njunction 295 nmjunction 2003 nmmetal 800 nmPMOS sourcep_srcjunction 2003 nmoxide 29 nmpoly 400 nmoxide 600 nmPMOS gatep_gatejunction 295 nmjunction 2003 nmmetal 800 nmPMOS drainp_drnjunction 2008 nmoxide 566 nmoxide 600 nmfield, eastfield_eacross: 27.0 µm wide · down: 1 µm = 78 px

Transistors

DeviceGateOxideVtWindowEffective lengthSource junctionChannel cm⁻³Idsat µA/µm
NMOS, n+ poly gaten+29 nm-0.16 V[0.50, 0.90]1090 of 1500 nm273 nm-1.0e15330
PMOS, p+ poly gate, in the n-wellp+29 nm-0.66 V[-0.90, -0.50]1058 of 1500 nm295 nm3.6e16149
03000 nm1e211e14
NMOS, n+ poly gate: net doping under the gate
03000 nm1e211e14
PMOS, p+ poly gate, in the n-well: net doping under the gate
n-typep-type

Wafer

goodkilled by a defectthreshold out of windowdefect
Wafer150 mm, 3 mm edge excluded
Die5.0 × 5.0 mm
Whole die576
Good die0 (0.0%)
Defect yield88.4% (67 killed)
Parametric yield0.0% (576 out of window)
Defect density0.660 /cm² with the edge ring
Closed-form yieldPoisson 84.8% · Murphy 85.0% · negative binomial 85.3%

Fab line

80 lots of 25 wafers through 35 operations: 3.5 days a lot (3.8 at the 90th percentile) against 2.4 days of process, 1.4× raw. 3.73 lots a day, 652 wafers a week, 324 wafers in the line.

Tool groupTools × loadBusyMean waitLots a run
oxidation and anneal furnace6 × 4 lots 64%0.2 h1.01
LPCVD tube2 × 4 lots 59%0.3 h1.02
sputter coater1 × 1 lot 23%0.0 h1.00
litho cell2 × 1 lot 37%0.1 h1.00
plasma etcher2 × 1 lot 61%0.3 h1.00
wet bench2 × 2 lots 18%0.0 h1.00
ion implanter (bottleneck)1 × 1 lot 64%1.1 h1.00
resist asher2 × 1 lot 48%0.0 h1.00

Cost

Blank wafer$40.00
Tool time$214.84 a wafer
Masks$3.50 a wafer
Per wafer$258.34
Per good dieno good die
Process steps (35)
  1. init_ox oxidize dry oxide now 42 nm on 10 of 10 columns screen oxide for the well implant
  2. nwell_pattern pattern NWELL open over 5 of 10 columns open the n-well
  3. nwell_implant implant phosphorus 3.5e12 cm⁻² at 150 keV (range 186 nm) reached silicon in 5 of 10 columns phosphorus for the n-well
  4. nwell_strip strip resist stripped from 5 of 10 columns
  5. nwell_drive anneal 1100 °C for 300 min spreads boron 740 nm, phosphorus 715 nm, arsenic 237 nm drive the well deep
  6. init_ox_etch etch oxide cleared from 10 of 10 columns back to bare silicon
  7. pad_ox oxidize dry oxide now 37 nm on 10 of 10 columns pad oxide under the nitride
  8. nitride deposit 100 nm of nitride over every column LPCVD nitride: the oxidation mask
  9. active_pattern pattern ACTIVE open over 4 of 10 columns
  10. nitride_etch etch nitride cleared from 4 of 10 columns nitride off the field
  11. active_strip strip resist stripped from 6 of 10 columns
  12. field_ox oxidize wet oxide now 615 nm on 4 of 10 columns LOCOS: thick oxide where the nitride is gone
  13. nitride_strip strip nitride stripped from 6 of 10 columns hot phosphoric acid
  14. pad_etch etch 50 nm off the oxide on 10 of 10 columns pad oxide off the active areas
  15. gate_ox oxidize dry oxide now 29–566 nm on 10 of 10 columns the gate dielectric
  16. poly deposit 400 nm of poly over every column undoped LPCVD polysilicon
  17. poly_pattern pattern POLY open over 8 of 10 columns
  18. poly_etch etch poly cleared from 8 of 10 columns
  19. poly_strip strip resist stripped from 2 of 10 columns
  20. nplus_pattern pattern NPLUS open over 3 of 10 columns
  21. nplus_implant implant phosphorus 5.0e15 cm⁻² at 60 keV (range 74 nm) reached silicon in 2 of 10 columns NMOS source/drain, and the NMOS gate goes n+
  22. nplus_strip strip resist stripped from 7 of 10 columns
  23. pplus_pattern pattern PPLUS open over 3 of 10 columns
  24. pplus_implant implant boron 3.0e15 cm⁻² at 30 keV (range 99 nm) reached silicon in 2 of 10 columns PMOS source/drain, and the PMOS gate goes p+
  25. pplus_strip strip resist stripped from 7 of 10 columns
  26. ild deposit 600 nm of oxide over every column deposited oxide between poly and metal
  27. reflow anneal 950 °C for 30 min spreads boron 39 nm, phosphorus 34 nm, arsenic 13 nm flows the oxide and activates the implants
  28. contact_pattern pattern CONTACT open over 4 of 10 columns
  29. contact_etch etch oxide cleared from 4 of 10 columns through the oxide to the source and drain
  30. contact_strip strip resist stripped from 6 of 10 columns
  31. metal deposit 800 nm of metal over every column sputtered aluminium; minutes are per wafer
  32. metal_pattern pattern METAL1 open over 6 of 10 columns
  33. metal_etch etch metal cleared from 6 of 10 columns
  34. metal_strip strip resist stripped from 4 of 10 columns
  35. sinter anneal 450 °C for 30 min spreads boron 0 nm, phosphorus 0 nm, arsenic 0 nm forming-gas anneal: ohmic contacts, fewer interface traps

Assumptions

  • Each column of the cut line is uniform and independent: no bird's beak, lateral diffusion or etch undercut.
  • Effective channel length is the drawn length less 1.5 times the source junction depth.
  • Dopants diffuse at their intrinsic rates; no segregation into growing oxide, no enhanced diffusion.
  • Implants follow tabulated LSS ranges with no channelling; films stop ions by assumed ratios to silicon.
  • Thresholds are long-channel, from the top 100 nm of the channel, with 1e10 cm⁻² fixed oxide charge.
  • Mobilities, tool rates, prices and mask life are assumed round figures.
  • Tool availability stretches every run; there are no discrete breakdowns or maintenance windows.
  • Defect density, clustering and the dirtier edge ring are assumed.

This page reads the bundled runs from CRE8VIRTUAL's virtual-wafer-fab. Nothing is stored, sent or fabricated.