Skip to content
1 viewer
Circuits

Wafer Fab TwinCRE8VIRTUAL's wafer-fab twin runs one recipe three ways: its steps build a cut line across the wafer, the same steps run as lots through a simulated fab line, and the wafer's die are drawn against particles and gate-stack spread. This page reads the bundled runs and recomputes each verdict from its checks.

One CMOS recipe through the cross-section, the fab line and the wafer.

Status
watch
NMOS Vt
0.70 V
PMOS Vt
-0.71 V
Die yield
62%
Cycle time
16.3 days
Per good die
$3.48

watch A home fab: 2-inch wafers, a tube furnace, masks printed on film, implants sent out. Its 50 nm gate oxide takes a lighter well and threshold implant than the pilot line's.

Checks

27 pass, 1 watch, 0 fault. The run is its worst check.

StatusSubjectCheckReading
watchdie yieldyield.total81 good of 130 whole die
passn-welllitho.NWELL20000 nm drawn against 3093 nm resolved; 5000 nm margin against 2000 nm overlay
passactive area (opens the field)litho.ACTIVE20000 nm drawn against 3093 nm resolved; 5000 nm margin against 2000 nm overlay
passNMOS threshold adjustlitho.VTN20000 nm drawn against 3093 nm resolved; 5000 nm margin against 2000 nm overlay
passpolysilicon gate (opens all but the gates)litho.POLY10000 nm drawn against 3093 nm resolved; 5000 nm margin against 2000 nm overlay
passn+ source/drainlitho.NPLUS20000 nm drawn against 3093 nm resolved; 5000 nm margin against 2000 nm overlay
passp+ source/drainlitho.PPLUS20000 nm drawn against 3093 nm resolved; 5000 nm margin against 2000 nm overlay
passcontactlitho.CONTACT10000 nm drawn against 3093 nm resolved; 5000 nm margin against 2000 nm overlay
passmetal 1 (opens all but the contacts)litho.METAL120000 nm drawn against 3093 nm resolved; 5000 nm margin against 2000 nm overlay
passfield oxideisolation.field_oxidethinnest field oxide 571 nm; 300 nm keeps a metal line over it from turning the field on
passNMOS, n+ poly gatenmos.gaten+ poly gate; a nmos wants n+
passNMOS, n+ poly gatenmos.channelchannel p-type at 1.6e16 cm⁻³
passNMOS, n+ poly gatenmos.thresholdVt 0.70 V in [0.50, 0.90]
passNMOS, n+ poly gatenmos.junctionsource junction 250 nm deep
passNMOS, n+ poly gatenmos.leff9625 nm effective of 10000 nm drawn
passNMOS, n+ poly gatenmos.oxide_field1.0 MV/cm across 50 nm at 5.0 V
passNMOS, n+ poly gatenmos.contactsmetal on the silicon of source and drain
passPMOS, p+ poly gate, in the n-wellpmos.gatep+ poly gate; a pmos wants p+
passPMOS, p+ poly gate, in the n-wellpmos.channelchannel n-type at 1.5e16 cm⁻³
passPMOS, p+ poly gate, in the n-wellpmos.thresholdVt -0.71 V in [-0.90, -0.50]
passPMOS, p+ poly gate, in the n-wellpmos.junctionsource junction 284 nm deep
passPMOS, p+ poly gate, in the n-wellpmos.leff9574 nm effective of 10000 nm drawn
passPMOS, p+ poly gate, in the n-wellpmos.oxide_field1.0 MV/cm across 50 nm at 5.0 V
passPMOS, p+ poly gate, in the n-wellpmos.contactsmetal on the silicon of source and drain
passbottleneckline.utilizationthe oxidation and anneal furnace group runs 75% busy; queues climb steeply past 85%
passcycle timeline.x_factora lot takes 391 h against 332 h of process: 1.2x
passline loadline.steadythe last quarter of lots took 0.94x as long as the first
passparametric yieldyield.parametric127 of 130 die land every threshold in its window

Cross-section

proximity mask aligner, 405 nm, 10 µm gap, manual alignment at 10000 nm drawn features: resolves 3093 nm, overlays to 2000 nm. The silicon is banded by type between its junctions; dashed lines are junctions.

oxidenitridepolyresistmetaln-type siliconp-type silicon
oxide 571 nmoxide 600 nmfield, westfield_wjunction 250 nmmetal 800 nmNMOS sourcen_srcoxide 50 nmpoly 400 nmoxide 600 nmNMOS gaten_gatejunction 250 nmmetal 800 nmNMOS drainn_drnoxide 571 nmoxide 600 nmfield over the p substratefield_mid_pjunction 1766 nmoxide 571 nmoxide 600 nmfield over the n-wellfield_mid_njunction 284 nmjunction 1759 nmmetal 800 nmPMOS sourcep_srcjunction 1759 nmoxide 50 nmpoly 400 nmoxide 600 nmPMOS gatep_gatejunction 284 nmjunction 1759 nmmetal 800 nmPMOS drainp_drnjunction 1766 nmoxide 571 nmoxide 600 nmfield, eastfield_eacross: 180.0 µm wide · down: 1 µm = 84 px

Transistors

DeviceGateOxideVtWindowEffective lengthSource junctionChannel cm⁻³Idsat µA/µm
NMOS, n+ poly gaten+50 nm0.70 V[0.50, 0.90]9625 of 10000 nm250 nm-1.6e1630
PMOS, p+ poly gate, in the n-wellp+50 nm-0.71 V[-0.90, -0.50]9574 of 10000 nm284 nm1.5e1613
03000 nm1e211e14
NMOS, n+ poly gate: net doping under the gate
03000 nm1e211e14
PMOS, p+ poly gate, in the n-well: net doping under the gate
n-typep-type

Wafer

goodkilled by a defectthreshold out of windowdefect
Wafer51 mm, 3 mm edge excluded
Die3.0 × 3.0 mm
Whole die130
Good die81 (62.3%)
Defect yield63.8% (47 killed)
Parametric yield97.7% (3 out of window)
Defect density8.253 /cm² with the edge ring
Closed-form yieldPoisson 47.6% · Murphy 49.8% · negative binomial 57.4%

Fab line

30 lots of 4 wafers through 38 operations: 16.3 days a lot (17.6 at the 90th percentile) against 13.8 days of process, 1.2× raw. 0.82 lots a day, 23 wafers a week, 54 wafers in the line.

Tool groupTools × loadBusyMean waitLots a run
oxidation and anneal furnace (bottleneck)1 × 1 lot 75%6.3 h1.00
LPCVD tube1 × 1 lot 26%0.4 h1.00
sputter coater1 × 1 lot 2%0.0 h1.00
litho cell1 × 1 lot 14%0.1 h1.00
plasma etcher1 × 1 lot 6%0.0 h1.00
wet bench1 × 1 lot 7%0.0 h1.00
ion implanter1 × 1 lot 4%0.0 h1.00
resist asher1 × 1 lot 6%0.0 h1.00

Cost

Blank wafer$12.00
Tool time$267.91 a wafer
Masks$1.60 a wafer
Per wafer$281.51
Per good die$3.48
Process steps (38)
  1. init_ox oxidize dry oxide now 42 nm on 10 of 10 columns screen oxide for the well implant
  2. nwell_pattern pattern NWELL open over 5 of 10 columns open the n-well
  3. nwell_implant implant phosphorus 1.5e12 cm⁻² at 150 keV (range 186 nm) reached silicon in 5 of 10 columns phosphorus for the n-well
  4. nwell_strip strip resist stripped from 5 of 10 columns
  5. nwell_drive anneal 1100 °C for 300 min spreads boron 740 nm, phosphorus 715 nm, arsenic 237 nm drive the well deep
  6. init_ox_etch etch oxide cleared from 10 of 10 columns back to bare silicon
  7. pad_ox oxidize dry oxide now 37 nm on 10 of 10 columns pad oxide under the nitride
  8. nitride deposit 100 nm of nitride over every column LPCVD nitride: the oxidation mask
  9. active_pattern pattern ACTIVE open over 4 of 10 columns
  10. nitride_etch etch nitride cleared from 4 of 10 columns nitride off the field
  11. active_strip strip resist stripped from 6 of 10 columns
  12. field_ox oxidize wet oxide now 615 nm on 4 of 10 columns LOCOS: thick oxide where the nitride is gone
  13. nitride_strip strip nitride stripped from 6 of 10 columns hot phosphoric acid
  14. pad_etch etch 50 nm off the oxide on 10 of 10 columns pad oxide off the active areas
  15. gate_ox oxidize dry oxide now 50–571 nm on 10 of 10 columns the gate dielectric
  16. vtn_pattern pattern VTN open over 3 of 10 columns
  17. vtn_implant implant boron 2.0e11 cm⁻² at 25 keV (range 82 nm) reached silicon in 3 of 10 columns boron to raise the NMOS threshold
  18. vtn_strip strip resist stripped from 7 of 10 columns
  19. poly deposit 400 nm of poly over every column undoped LPCVD polysilicon
  20. poly_pattern pattern POLY open over 8 of 10 columns
  21. poly_etch etch poly cleared from 8 of 10 columns
  22. poly_strip strip resist stripped from 2 of 10 columns
  23. nplus_pattern pattern NPLUS open over 3 of 10 columns
  24. nplus_implant implant phosphorus 5.0e15 cm⁻² at 60 keV (range 74 nm) reached silicon in 2 of 10 columns NMOS source/drain, and the NMOS gate goes n+
  25. nplus_strip strip resist stripped from 7 of 10 columns
  26. pplus_pattern pattern PPLUS open over 3 of 10 columns
  27. pplus_implant implant boron 3.0e15 cm⁻² at 30 keV (range 99 nm) reached silicon in 2 of 10 columns PMOS source/drain, and the PMOS gate goes p+
  28. pplus_strip strip resist stripped from 7 of 10 columns
  29. ild deposit 600 nm of oxide over every column deposited oxide between poly and metal
  30. reflow anneal 950 °C for 30 min spreads boron 39 nm, phosphorus 34 nm, arsenic 13 nm flows the oxide and activates the implants
  31. contact_pattern pattern CONTACT open over 4 of 10 columns
  32. contact_etch etch oxide cleared from 4 of 10 columns through the oxide to the source and drain
  33. contact_strip strip resist stripped from 6 of 10 columns
  34. metal deposit 800 nm of metal over every column sputtered aluminium; minutes are per wafer
  35. metal_pattern pattern METAL1 open over 6 of 10 columns
  36. metal_etch etch metal cleared from 6 of 10 columns
  37. metal_strip strip resist stripped from 4 of 10 columns
  38. sinter anneal 450 °C for 30 min spreads boron 0 nm, phosphorus 0 nm, arsenic 0 nm forming-gas anneal: ohmic contacts, fewer interface traps

Assumptions

  • Each column of the cut line is uniform and independent: no bird's beak, lateral diffusion or etch undercut.
  • Effective channel length is the drawn length less 1.5 times the source junction depth.
  • Dopants diffuse at their intrinsic rates; no segregation into growing oxide, no enhanced diffusion.
  • Implants follow tabulated LSS ranges with no channelling; films stop ions by assumed ratios to silicon.
  • Thresholds are long-channel, from the top 100 nm of the channel, with 1e10 cm⁻² fixed oxide charge.
  • Mobilities, tool rates, prices and mask life are assumed round figures.
  • Tool availability stretches every run; there are no discrete breakdowns or maintenance windows.
  • Defect density, clustering and the dirtier edge ring are assumed.

This page reads the bundled runs from CRE8VIRTUAL's virtual-wafer-fab. Nothing is stored, sent or fabricated.